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EL8100, EL8101
Data Sheet August 10, 2007 FN7103.8
200MHz Rail-to-Rail Amplifiers
The EL8100 and EL8101 represent single rail-to-rail amplifiers with a -3dB bandwidth of 200MHz and slew rate of 200V/s. Running off a very low 2mA supply current, the EL8100 and EL8101 also feature inputs that go to 0.15V below the VS- rail. The EL8100 includes a fast-acting disable/power-down circuit. With a 25ns disable and a 200ns enable, the EL8100 is ideal for multiplexing applications. The EL8100 and EL8101 are designed for a number of general purpose video, communication, instrumentation, and industrial applications. The EL8100 is available in 8 Ld SO and 6 Ld SOT-23 packages and the EL8101 is available in a 5 Ld SOT-23 package. All are specified for operation over the -40C to +85C temperature range.
Features
* 200MHz -3dB bandwidth * 200V/s slew rate * Low supply current = 2mA * Supplies from 3V to 5.0V * Rail-to-rail output * Input to 0.15V below VS* Fast 25ns disable (EL8100 only) * Low cost * Pb-Free available (RoHS compliant)
Applications
* Video amplifiers * Portable/hand-held products
Ordering Information
PART NUMBER EL8100IS EL8100IS-T7* EL8100IS-T13* EL8100ISZ (Note) EL8100ISZ-T7* (Note) EL8100ISZ-T13* (Note) EL8100IW-T7* EL8100IW-T7A* EL8100IWZ-T7* (Note) PART MARKING 8100IS 8100IS 8100IS 8100ISZ 8100ISZ 8100ISZ 6 6 BASA PACKAGE 8 Ld SO 8 Ld SO 8 Ld SO 8 Ld SO (Pb-Free) 8 Ld SO (Pb-Free) 8 Ld SO (Pb-Free) 6 Ld SOT-23 6 Ld SOT-23 6 Ld SOT-23 (Pb-free) 6 Ld SOT-23 (Pb-free) 5 Ld SOT-23 5 Ld SOT-23 5 Ld SOT-23 (Pb-Free) 5 Ld SOT-23 (Pb-Free) PKG. DWG. # MDP0027 MDP0027 MDP0027 MDP0027
* Communications devices
Pinouts
EL8100 (8 LD SO) TOP VIEW
NC 1 8 ENABLE + 7 VS+ 6 OUT 5 NC
MDP0027 MDP0027 MDP0038 MDP0038 MDP0038 MDP0038
IN- 2 IN+ 3 VS- 4
EL8100IWZ-T7A* BASA (Note) EL8101IW-T7* EL8101IW-T7A* EL8101IWZ-T7* (Note) 3 3 BATA
EL8100 (6 LD SOT-23) TOP VIEW
OUT 1 6 VS+ +5 ENABLE 4 IN-
MDP0038
VS- 2
MDP0038 MDP0038 MDP0038
IN+ 3
EL8101IWZ-T7A* BATA (Note)
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
OUT 1 VS- 2 IN+ 3
EL8101 (5 LD SOT-23) TOP VIEW
5 VS+ +4 IN-
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2003-2005, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
EL8100, EL8101
Absolute Maximum Ratings (TA = 25C)
Supply Voltage from VS+ to VS- . . . . . . . . . . . . . . . . . . . . . . . . 5.5V Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . VS+ +0.3V to VS- -0.3V Differential Input Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V Continuous Output Current . . . . . . . . . . . . . . . . . . . . . . . . . . . 40mA
Thermal Information
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Curves Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65C to +125C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +125C Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty.
IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typ values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
Electrical Specifications
PARAMETER
VS+ = 5V, VS- = GND, TA = +25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. CONDITIONS MIN (Note 1) TYP MAX (Note 1) UNIT
DESCRIPTION
INPUT CHARACTERISTICS VOS TCVOS IB IOS TCIOS CMRR CMIR RIN CIN AVOL Offset Voltage Offset Voltage Temperature Coefficient Measured from TMIN to TMAX Input Bias Current Input Offset Current Input Bias Current Temperature Coefficient Common Mode Rejection Ratio Common Mode Input Range Input Resistance Input Capacitance Open Loop Gain VOUT = +1.5V to +3.5V, RL = 1k to GND VOUT = +1.5V to +3.5V, RL = 150 to GND OUTPUT CHARACTERISTICS ROUT VOP Output Resistance Positive Output Voltage Swing AV = +1 RL = 1k RL = 150 VON Negative Output Voltage Swing RL = 150 RL = 1k IOUT ISC (source) ISC (sink) Linear Output Current Short Circuit Current Short Circuit Current RL = 10 RL = 10 60 120 4.85 4.6 30 4.9 4.7 100 35 65 70 140 150 50 m V V mV mV mA mA mA 75 Common Mode VIN = 0V VIN = 0V Measured from TMIN to TMAX VCM = -0.15V to +3.5V 70 VS- -0.15 16 0.5 90 80 -2.1 -6 -0.8 3 -1.5 0.2 2 90 VS+ -1.5 0.55 +6 mV V/C A A nA/C dB V M pF dB dB
POWER SUPPLY PSRR IS-ON IS-OFF Power Supply Rejection Ratio Supply Current - Enabled Supply Current - Disabled VS+ = 4.5V to 5.5V 75 100 2 30 2.4 dB mA A
ENABLE (EL8100 ONLY) tEN tDS Enable Time Disable Time 200 25 ns ns
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FN7103.8 August 10, 2007
EL8100, EL8101
Electrical Specifications
PARAMETER VIH-ENB VIL-ENB IIH-ENB IIL-ENB VS+ = 5V, VS- = GND, TA = +25C, VCM = 2.5V, RL to 2.5V, AV = 1, Unless Otherwise Specified. (Continued) CONDITIONS MIN (Note 1) TYP 0.8 2 8.6 0.01 MAX (Note 1) UNIT V V A A
DESCRIPTION ENABLE Pin Voltage for Power-up ENABLE Pin Voltage for Shut-down ENABLE Pin Input Current High ENABLE Pin Input for Current Low
AC PERFORMANCE BW -3dB Bandwidth AV = +1, RF = 0, CL = 5pF AV = -1, RF = 1k, CL = 5pF AV = +2, RF = 1k, CL = 5pF AV = +10, RF = 1k, CL = 5pF BW Peak GBWP PM SR tR tF OS tPD tS dG dP eN iN+ iNNOTE: 1. Parts are 100% tested at +25C. Over-temperature limits established by characterization and are not production tested. 0.1dB Bandwidth Peaking Gain Bandwidth Product Phase Margin Slew Rate Rise Time Fall Time Overshoot Propagation Delay 0.1% Settling Time Differential Gain Differential Phase Input Noise Voltage Positive Input Noise Current Negative Input Noise Current RL = 1k, CL = 5pF AV = 2, RL = 100, VOUT = 0.5V to 4.5V 2.5VSTEP, 20% - 80% 2.5VSTEP, 20% - 80% 200mV step 200mV step 200mV step AV = +2, RF = 1k, RL = 150 AV = +2, RF = 1k, RL = 150 f = 10kHz f = 10kHz f = 10kHz 160 AV = +1, RF = 0, CL = 5pF AV = +1, RF = 1k, CL = 5pF 200 90 90 10 20 1 100 55 200 8 7 10 2 20 0.035 0.05 10 1 0.8 MHz MHz MHz MHz MHz dB MHz V/s ns ns % ns ns % nV/Hz pA/Hz pA/Hz
Pin Descriptions
PIN EL8100IS 1 2 3 4 5 6 7 8 1 6 5 1 5 4 3 2 4 3 2 EL8100IW EL8101IW NC ININ+ VSNC OUT VS+ ENABLE Not connected Inverting input Non-inverting input Negative power supply Not connected Amplifier output Positive power supply Enable and disable input FUNCTION
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FN7103.8 August 10, 2007
EL8100, EL8101 Simplified Schematic Diagram
VS+ I1 I2 Q5 R3 R1 IN+ Q1 Q2 R2 INDIFFERENTIAL TO SINGLE ENDED DRIVE GENERATOR Q3 Q4 Q8 R4 R5 VSR9 OUT R6 R7 VBIAS1 R8 Q7
Q6
VBIAS2
Typical Performance Curves
4 VS = 5V AV = 1 RL = 1k CL = 5pF 4 VS = 5V AV = 1 CL = 5pF
2 GAIN (dB)
VOP-P = 200mV GAIN (dB)
2
RL = 330
0 VOP-P = 1V -2 VOP-P = 2V -4 -6 100k
0 RL = 1k -2 RL = 100 -4
1M
10M FREQUENCY (Hz)
100M
1G
-6 100k
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 1. FREQUENCY RESPONSE FOR VARIOUS OUTPUT VOLTAGE LEVELS
FIGURE 2. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RLOAD
4 NORMALIZED GAIN (dB) NORMALIZED GAIN (dB) VS = 5V RL = 1k CL = 5pF AV = 2 0
4 VS = 5V RL = 1k CL = 5pF RF = 1k
2
AV = 1
2
AV = -5 AV = -2
0
-2
AV = 5
-2
AV = -10
-4
AV = 10
-4
-6 100k
1M
10M FREQUENCY (Hz)
100M
1G
-6 100k
1M
10M FREQUENCY (Hz)
100M
1G
FIGURE 3. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS NON-INVERTING GAINS
FIGURE 4. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS INVERTING GAINS
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FN7103.8 August 10, 2007
EL8100, EL8101 Typical Performance Curves (Continued)
5 CL = 15pF 3 GAIN (dB) CL = 11.5pF GAIN (dB) CL = 8.3pF CL = 5pF CL = 1.5pF 8 CL = 35pF 10 CL = 56pF
1
6 CL = 15pF 4 VS = 5V AV = 2 RL = 1k RF = RG = 1k 1M CL = 5pF
-1 VS = 5V -3 AV = 1 RL = 1k VOP-P = 200mV -5 100k 1M
2
10M
100M
1G
0 100k
10M FREQUENCY (Hz)
100M
1G
FREQUENCY (Hz)
FIGURE 5. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL
FIGURE 6. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS CL
10
110 RL = 1k
405
8 RF = RG = 2k GAIN (dB) 6 RF = RG = 500 VS = 5V AV = 2 RL = 1k CL = 5pF 1M 10M
RF = RG = 1k GAIN (dB)
70 RL = 150 30 RL = 150 RL = 1k
315 PHASE ()
225
4
-10
135
2
-50
45
0 100k
100M
1G
-90 1k
10k
100k
1M
10M
100M
-45 1G
FREQUENCY (Hz)
FREQUENCY (Hz)
FIGURE 7. SMALL SIGNAL FREQUENCY RESPONSE FOR VARIOUS RF AND RG
FIGURE 8. OPEN LOOP GAIN AND PHASE vs FREQUENCY
-10
230 210 AV = 1
-30 BANDWIDTH (MHz) CMRR (dB)
190 170 150 130 110 90 70 RL = 1k CL = 5pF 3.5 4.0
-50
-70
-90
AV = 2 4.5 VS (V) 5.0 5.5
-110 100k
1M
10M
100M
50 3.0
FREQUENCY (Hz)
FIGURE 9. COMMON-MODE REJECTION RATIO vs FREQUENCY
FIGURE 10. SMALL SIGNAL BANDWIDTH vs SUPPLY VOLTAGE
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FN7103.8 August 10, 2007
EL8100, EL8101 Typical Performance Curves (Continued)
100 2.5
IMPEDANCE ()
10 PEAKING (dB)
2.0
1.5
1
1.0 AV = 1 RL = 1k CL = 5pF 3.5 4.0 VS (V) 4.5 5.0 5.5
0.1
0.5
0.01 10k
100k
1M FREQUENCY (Hz)
10M
100M
0 3.0
FIGURE 11. OUTPUT IMPEDANCE vs FREQUENCY
FIGURE 12. SMALL SIGNAL PEAKING vs SUPPLY VOLTAGE
-10
-45 VS = 5V RL = 1k CL = 5pF AV = 2
z 0MH
-30 DISTORTION (dBc) PSRR (dB) PSRR-
-55
-50
-65
MHz @10 HD3 Hz HD3@5M
@1 HD2
-70
PSRR+
-75
z HD2@5MH
HD2@
1MHz
-90
-85
HD3@1MHz -110 1k -95 10k 100k 1M 10M 100M 1 2 3 VOP-P (V) 4 5 FREQUENCY (Hz)
FIGURE 13. POWER SUPPLY REJECTION RATIO vs FREQUENCY
FIGURE 14. HARMONIC DISTORTION vs OUTPUT VOLTAGE
-10 VS = 5V AV = 1 RL = 1k CL = 5pF
-30 -40 DISTORTION (dBc) -50 -60 -70 -80 -90
=2 @AV D2 H
-30 GAIN (dB)
VS = 5V RL = 1k VO = 1VP-P for AV = 1 VO = 2VP-P for AV = 2
=1 AV
-50
-70
H
@ D2
-90
2 AV= 3@ HD HD3@AV=1
-110 1k
-100 10k 100k 1M 10M 100M 1G 1 10 FREQUENCY (MHz) 40 FREQUENCY (Hz)
FIGURE 15. DISABLED OUTPUT ISOLATION FREQUENCY RESPONSE
FIGURE 16. HARMONIC DISTORTION vs FREQUENCY
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FN7103.8 August 10, 2007
EL8100, EL8101 Typical Performance Curves (Continued)
-60 VOLTAGE NOISE (nV/Hz) CURRENT NOISE (pA/Hz) -65 DISTORTION (dBc) -70 -75 -80 -85 -90 -95
HD 3@
HD
1k
H D 2@
AV=
AV =2
100 eN
2
3@ A
HD2@A =1 V
1
10
V=
VS = 5V VO = 1VP-P for AV = 1 VO = 2VP-P for AV = 2 1K RLOAD () 2K
1
IN+ IN-
-100 100
0.1 10
100
1k
10k
100k
1M
10M
FREQUENCY (Hz)
FIGURE 17. HARMONIC DISTORTION vs LOAD RESISTANCE
FIGURE 18. VOLTAGE AND CURRENT NOISE vs FREQUENCY
VS = 5V, AV = 1, RL = 1k TO 2.5V
VS = 5V, AV = 5, RL = 1k TO 2.5V
5
5
2.5
2.5
0
0
10ns/DIV
2s/DIV
FIGURE 19. LARGE SIGNAL TRANSIENT RESPONSE
FIGURE 20. OUTPUT SWING
VS = 5V, AV = 1, RL = 1k TO 2.5V CL=5pF
VS = 5V, AV = 5, RL = 1k TO 2.5V
5 2.6
2.5
2.5
2.4 0
10ns/DIV
2s/DIV
FIGURE 21. SMALL SIGNAL TRANSIENT RESPONSE
FIGURE 22. OUTPUT SWING
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FN7103.8 August 10, 2007
EL8100, EL8101 Typical Performance Curves (Continued)
VS = 2.5V, AV = 1, RL = 1k VS = 2.5V, AV = 1, RL = 1k
CH1 ENABLE INPUT CH1 ENABLE INPUT
CH2 CH2 OUTPUT VOUT
CH1, CH2, 0.5V/DIV, M = 20ns
CH1, CH2, 1V/DIV, M = 100ns
FIGURE 23. DISABLED RESPONSE
FIGURE 24. ENABLED RESPONSE
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD 1.4 POWER DISSIPATION (W) POWER DISSIPATION (W) 1.2 1.0 909mW 0.8 0.6 0.4 0.2 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +230C/W 435mW SO8 JA = +110C/W 1.0 0.9 0.8
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
0.7 625mW 0.6 0.5 0.4 0.3 0.2 0.1 0 0 25 50 75 85 100 125 150 AMBIENT TEMPERATURE (C) SOT23-5/6 JA = +256C/W 391mW SO8 JA = +160C/W
FIGURE 25. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 26. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
Description of Operation and Application Information
Product Description
The EL8100, EL8101 are wide bandwidth, single supply, low power and rail-to-rail output voltage feedback operational amplifiers. Both amplifiers are internally compensated for closed loop gain of +1 of greater. Connected in voltage follower mode and driving a 1k load, the EL8100, EL8101 have a -3dB bandwidth of 200MHz. Driving a 150 load, the bandwidth is about 130MHz while maintaining a 200V/s slew rate. The EL8100 is available with a power down pin to reduce power to 30A typically while the amplifier is disabled.
The amplifiers have an input common mode voltage range from 0.15V below the negative supply (VS- pin) to within 1.5V of the positive supply (VS+ pin). If the input signal is outside the above specified range, it will cause the output signal to be distorted. The output of the EL8100, EL8101 can swing rail to rail. As the load resistance becomes lower, the ability to drive close to each rail is reduced. For the load resistor 1k, the output swing is about 4.9V at a 5V supply. For the load resistor 150, the output swing is about 4.6V.
Choice of Feedback Resistor and Gain Bandwidth Product
For applications that require a gain of +1, no feedback resistor is required. Just short the output pin to the inverting input pin. For gains greater than +1, the feedback resistor forms a pole with the parasitic capacitance at the inverting input. As this pole becomes smaller, the amplifier's phase margin is reduced. This causes ringing in the time domain
FN7103.8 August 10, 2007
Input, Output and Supply Voltage Range
The EL8100, EL8101 have been designed to operate with a single supply voltage from 3V to 5.0V. Split supplies can also be used as long as their total voltage is within 3V to 5.0V.
8
EL8100, EL8101
and peaking in the frequency domain. Therefore, RF has some maximum value that should not be exceeded for optimum performance. If a large value of RF must be used, a small capacitor in the few Pico farad range in parallel with RF can help to reduce the ringing and peaking at the expense of reducing the bandwidth. As far as the output stage of the amplifier is concerned, the output stage is also a gain stage with the load. RF and RG appear in parallel with RL for gains other than +1. As this combination gets smaller, the bandwidth falls off. Consequently, RF also has a minimum value that should not be exceeded for optimum performance. For gain of +1, RF=0 is optimum. For the gains other than +1, optimum response is obtained with RF between 300 to 1k. The EL8100, EL8101 have a gain bandwidth product of 100MHz. For gains 5, its bandwidth can be predicted by Equation 1:
Gain x BW = 100MHz (EQ. 1)
on time is about 200ns. When disabled, the amplifier's supply current is reduced to 30A typically, thereby effectively eliminating the power consumption. The amplifier's power down can be controlled by standard TTL or CMOS signal levels at the ENABLE pin. The applied logic signal is relative to VS- pin. Letting the ENABLE pin float or applying a signal that is less than 0.8V above VS- will enable the amplifier. The amplifier will be disabled when the signal at ENABLE pin is 2V above VS-.
Output Drive Capability
The EL8100, EL8101 do not have internal short circuit protection circuitry. They have a typical short circuit current of 70mA sourcing and 140mA sinking for the output is connected to half way between the rails with a 10 resistor. If the output is shorted indefinitely, the power dissipation could easily increase such that the part will be destroyed. Maximum reliability is maintained if the output current never exceeds 40mA. This limit is set by the design of the internal metal interconnections.
Video Performance
For good video performance, an amplifier is required to maintain the same output impedance and the same frequency response as DC levels are changed at the output. This is especially difficult when driving a standard video load of 150, because the change in output current with DC level. Special circuitry has been incorporated in the EL8100, EL8101 to reduce the variation of the output impedance with the current output. This results in dG and dP specifications of 0.03% and 0.05, while driving 150 at a gain of 2. Driving high impedance loads would give a similar or better dG and dP performance.
Power Dissipation
With the high output drive capability of the EL8100, EL8101, it is possible to exceed the +125C absolute maximum junction temperature under certain load current conditions. Therefore, it is important to calculate the maximum junction temperature for the application to determine if the load conditions or package types need to be modified for the amplifier to remain in the safe operating area. The maximum power dissipation allowed in a package is determined according to Equation 2:
T JMAX - T AMAX PD MAX = ------------------------------------------- JA (EQ. 2)
Driving Capacitive Loads and Cables
The EL8100, EL8101 can drive 15pF loads in parallel with 1k with less than 5dB of peaking at gain of +1. If less peaking is desired in applications, a small series resistor (usually between 5 to 50) can be placed in series with the output to eliminate most peaking. However, this will reduce the gain slightly. If the gain setting is greater than 1, the gain resistor RG can then be chosen to make up for any gain loss which may be created by the additional series resistor at the output. When used as a cable driver, double termination is always recommended for reflection-free performance. For those applications, a back-termination series resistor at the amplifier's output will isolate the amplifier from the cable and allow extensive capacitive drive. However, other applications may have high capacitive loads without a back-termination resistor. Again, a small series resistor at the output can help to reduce peaking.
Where: TJMAX = Maximum junction temperature TAMAX = Maximum ambient temperature JA = Thermal resistance of the package The maximum power dissipation actually produced by an IC is the total quiescent supply current times the total power supply voltage, plus the power in the IC due to the load, or: For sourcing, Equation 3:
V OUT PD MAX = V S x I SMAX + ( V S - V OUT ) x --------------R
L
(EQ. 3)
For sinking, Equation 4:
PD MAX = V S x I SMAX + ( V OUT - V S - ) x I LOAD (EQ. 4)
Where: VS = Total supply voltage ISMAX = Maximum quiescent supply current
Disable/Power-Down
The EL8100 can be disabled and placed its output in a high impedance state. The turn off time is about 25ns and the turn
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FN7103.8 August 10, 2007
EL8100, EL8101
VOUT = Maximum output voltage of the application RLOAD = Load resistance tied to ground ILOAD = Load current By setting the two PDMAX equations equal to each other, we can solve the output current and RLOAD to avoid the device overheat. and VIN2 is passed through to the output. The break-beforemake operation ensures that more than one amplifier isn't trying to drive the bus at the same time.
5V VIN 75 + VS+ VS75 1K 1k 75 VOUT
-
Power Supply Bypassing and Printed Circuit Board Layout
As with any high frequency device, a good printed circuit board layout is necessary for optimum performance. Lead lengths should be as sort as possible. The power supply pin must be well bypassed to reduce the risk of oscillation. For normal single supply operation, where the VS- pin is connected to the ground plane, a single 4.7F tantalum capacitor in parallel with a 0.1F ceramic capacitor from VS+ to GND will suffice. This same capacitor combination should be placed at each supply pin to ground if split supplies are to be used. In this case, the VS- pin becomes the negative supply rail. For good AC performance, parasitic capacitance should be kept to a minimum. Use of wire wound resistors should be avoided because of their additional series inductance. Use of sockets should also be avoided if possible. Sockets add parasitic inductance and capacitance that can result in compromised performance. Minimizing parasitic capacitance at the amplifier's inverting input pin is very important. The feedback resistor should be placed very close to the inverting input pin. Strip line design techniques are recommended for the signal traces.
FIGURE 27. SYNC PULSE REMOVER
1V VIN 0.5V 0V 1V VOUT 0.5V 0V
M = 10s/DIV
FIGURE 28. VIDEO SIGNAL
+2.5V B 2MHz 1VP-P 75 -2.5V +
-
Typical Applications
VIDEO SYNC PULSE REMOVER Many CMOS analog to digital converters have a parasitic latch up problem when subjected to negative input voltage levels. Since the sync tip contains no useful video information and it is a negative going pulse, we can chop it off. Figure 27 shows a gain of 2 connections for EL8100, EL8101. Figure 28 shows the complete input video signal applied at the input, as well as the output signal with the negative going sync pulse removed. MULTIPLEXER Besides the normal power down usage, the ENABLE pin of the EL8100 can be used for multiplexing applications. Figure 29 shows two EL8100s with the outputs tied together, driving a back terminated 75 video load. A 2VP-P 2MHz sine wave is applied to Amp A and a 1VP-P 2MHz sine wave is applied to Amp B. Figure 30 shows the ENABLE signal and the resulting output waveform at VOUT. Observe the break-before-make operation of the multiplexing. Amp A is on and VIN1 is passed through to the output when the ENABLE signal is low and turns off in about 25ns when the ENABLE signal is high. About 200ns later, Amp B turns on
FIGURE 29. TWO TO ONE MULTIPLEXER
A 2MHz 2VP-P 75 -2.5V 1K 1K +2.5V + 75 75 VOUT
-
1K 1k ENABLE
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FN7103.8 August 10, 2007
EL8100, EL8101
RF 1k 0V -0.5V ENABLE -1.5V -2.5V 1V 0V A B -1V R2 10k C2 220F RT 75 5V R1 10k C1 RG 47F 500 5V R3 C3 470F 75
VIN
-
VOUT
+ 75
M = 50ns/DIV
FIGURE 32. 5V SINGLE SUPPLY INVERTING VIDEO LINE DRIVER
FIGURE 30. ENABLE SIGNAL
SINGLE SUPPLY VIDEO LINE DRIVER The EL8100, EL8101 are wideband rail-to-rail output op amplifiers with large output current, excellent dG, dP, and low distortion that allow them to drive video signals in low supply applications. Figure 31 is the single supply non-inverting video line driver configuration and Figure 32 is the inverting video ling driver configuration. The signal is AC coupled by C1. R1 and R2 are used to level shift the input and output to provide the largest output swing. RF and RG set the AC gain. C2 isolates the virtual ground potential. RT and R3 are the termination resistors for the line. C1, C2 and C3 are selected big enough to minimize the droop of the luminance signal.
5V 5 4 NORMALIZED GAIN (dB) 3 2 1 0 -1 -2 -3 -4 -5 100K 1M 10M FREQUENCY (Hz) 100M 200M AV = -2 AV = 2
FIGURE 33. VIDEO LINE DRIVER FREQUENCY RESPONSE
VIN RT 75 C1 47F R2 10k R1 10k + R3 C3 470F 75 VOUT
-
75 RG 1k RF 1k C2 220F
FIGURE 31. 5V SINGLE SUPPLY NON INVERTING VIDEO LINE DRIVER
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FN7103.8 August 10, 2007
EL8100, EL8101 Small Outline Package Family (SO)
A D N (N/2)+1 h X 45
A E E1 PIN #1 I.D. MARK c SEE DETAIL "X"
1 B
(N/2) L1
0.010 M C A B e C H A2 GAUGE PLANE A1 0.004 C 0.010 M C A B b DETAIL X
SEATING PLANE L 4 4
0.010
MDP0027
SMALL OUTLINE PACKAGE FAMILY (SO) INCHES SYMBOL A A1 A2 b c D E E1 e L L1 h N NOTES: 1. Plastic or metal protrusions of 0.006" maximum per side are not included. 2. Plastic interlead protrusions of 0.010" maximum per side are not included. 3. Dimensions "D" and "E1" are measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994 SO-8 0.068 0.006 0.057 0.017 0.009 0.193 0.236 0.154 0.050 0.025 0.041 0.013 8 SO-14 0.068 0.006 0.057 0.017 0.009 0.341 0.236 0.154 0.050 0.025 0.041 0.013 14 SO16 (0.150") 0.068 0.006 0.057 0.017 0.009 0.390 0.236 0.154 0.050 0.025 0.041 0.013 16 SO16 (0.300") (SOL-16) 0.104 0.007 0.092 0.017 0.011 0.406 0.406 0.295 0.050 0.030 0.056 0.020 16 SO20 (SOL-20) 0.104 0.007 0.092 0.017 0.011 0.504 0.406 0.295 0.050 0.030 0.056 0.020 20 SO24 (SOL-24) 0.104 0.007 0.092 0.017 0.011 0.606 0.406 0.295 0.050 0.030 0.056 0.020 24 SO28 (SOL-28) 0.104 0.007 0.092 0.017 0.011 0.704 0.406 0.295 0.050 0.030 0.056 0.020 28 TOLERANCE MAX 0.003 0.002 0.003 0.001 0.004 0.008 0.004 Basic 0.009 Basic Reference Reference NOTES 1, 3 2, 3 Rev. M 2/07
12
FN7103.8 August 10, 2007
EL8100, EL8101 SOT-23 Package Family
e1 A N 6 4
MDP0038
D
SOT-23 PACKAGE FAMILY MILLIMETERS SYMBOL A A1 SOT23-5 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 5 SOT23-6 1.45 0.10 1.14 0.40 0.14 2.90 2.80 1.60 0.95 1.90 0.45 0.60 6 TOLERANCE MAX 0.05 0.15 0.05 0.06 Basic Basic Basic Basic Basic 0.10 Reference Reference Rev. F 2/07 NOTES:
E1 2 3
E
A2 b c
0.20 C
0.15 C D 2X 5 e B b NX 1 2 3 2X 0.20 M C A-B D
D E E1 e e1 L L1 N
0.15 C A-B 2X C D
1
3
A2 SEATING PLANE 0.10 C NX A1
1. Plastic or metal protrusions of 0.25mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25mm maximum per side are not included. 3. This dimension is measured at Datum Plane "H". 4. Dimensioning and tolerancing per ASME Y14.5M-1994. 5. Index area - Pin #1 I.D. will be located within the indicated zone (SOT23-6 only).
(L1)
H
6. SOT23-5 version has no center lead (shown as a dashed line).
A
GAUGE PLANE c L 0 +3 -0
0.25
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 13
FN7103.8 August 10, 2007

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